1. Field of the Invention
The present invention relates to a resistance defect assessment device, a resistance defect assessment method and a method for manufacturing a resistance defect assessment device, and more particularly to a monitoring device for detecting a resistance increase defect in a resistive element or a contact provided in a semiconductor integrated circuit device during the manufacture thereof, a method for assessing a resistance increase defect using such a monitoring device, and a method for manufacturing such a monitoring device.
2. Description of the Background Art
In recent years, the feature size of a semiconductor integrated circuit device has been reduced, and the degree of integration and the processing speed thereof have been increased. Moreover, the size (diameter) of a wafer used for manufacturing the same has been increased.
As the feature size of a semiconductor integrated circuit device is decreased and the degree of integration thereof is increased, the production yield thereof is decreased more significantly by a line-break defect or an inter-line shorting defect in a gate electrode wiring, a metal wiring, an impurity layer to be a source region and a drain region (hereinafter referred to as a “source/drain impurity layer”), a contact connecting a lower wiring layer with an upper wiring layer, or the like. Moreover, due to the increase in the degree of integration and the processing speed thereof, characteristics variations among transistors or resistive elements (e.g., gate electrode wirings, metal wirings or a source/drain impurity layer) provided therein also present a significant cause of a decrease in the production yield. Thus, in order to improve the production yield of a semiconductor integrated circuit device while realizing a high processing speed thereof, it may be necessary to suppress, particularly, the variations among the resistors (resistive elements), including the variations in the transistor characteristics.
Conventionally, complete line-break defects and inter-line shorting defects have been addressed as the primary defects in the gate electrode wiring of a transistor, the metal wiring on a transistor, etc. Moreover, the amount of line-break defect or shorting defect (the number of defects) has been measured in order to estimate the yield of a semiconductor integrated circuit device.
In a conventional method for assessing line-break defects and shorting defects, long wirings whose length is on the order of 10 cm to 1 m are routed to form a comb/serp pattern so as to assess the yield of the object layer (wiring layer) (see, for example, Charles Weber, “Standard Defect Monitor”, 1988 IEEE Proceedings on Microelectronic Test Structures, Vol. 1, No. 1, February 1988, pp. 114-119 (hereinafter referred to as “Reference 1”)).
FIG. 25 shows an example of a conventional comb/serp line pattern. Referring to FIG. 25, in the yield assessment method of Reference 1, the resistance between the comb pads is measured to detect a line-break defect, and the leak current between a comb pad and the serp pad is measured to detect a shorting defect. Particularly for the line-break defect, a very long line is virtually routed so as to allow for the yield assessment. Therefore, it only detects a complete line-break defect but does not detect a resistance increase (resistance variation) occurring in a portion of (at a certain point along) the line.
In another method proposed in the art for assessing a resistor variation, the dimension of the formed pattern is electrically measured so as to assess the influence of a dimensional variation in the gate electrode wiring, or the like (see, for example, Andrew Grenville, et al., “Electrical Critical Dimension Metrology for 100-nm Linewidths and Below”, In Optical Microlithography XIII, Proceedings of SPIE, Vol. 4000, 2000, pp. 452-459 (hereinafter referred to as “Reference 2”)). Such a dimensional variation leads to a resistor variation or a transistor characteristics variation, thus decreasing the yield. Therefore, assessment of the influence of a dimensional variation is also important.
A defect may occur even in a case where a gate electrode wiring, a metal wiring, a contact connecting an impurity layer with a wiring layer, or the like, is not completely broken, i.e., where a portion of such a component has an increased resistance (the resistance of the component is higher at a certain position than at other positions) even though the electrical connection thereof is maintained within the component. Such a defect may also cause a decrease in the yield or the reliability. The term “resistance increase defect (resistance variation defect)” or “soft-open defect” as used herein refers to such a defect where a component (a resistive element, a contact, etc.) has a locally-increased resistance (thereby also increasing the overall resistance of the resistive element) even though the component is not completely broken and the electrical connection therein is maintained. The term “line-break defect” or “hard-open defect” as used herein refers to a defect where a resistive element or a contact is completely broken.
Along with the recent reduction in the feature size of a semiconductor integrated circuit device and the increase in the degree of integration and the processing speed thereof, the delay time margin has been decreased, whereby even a resistance increase defect occurring at one position along a resistive element such as a line can cause a decrease in the yield and the reliability.
In the formation of a gate electrode wiring, for example, a silicide layer is typically formed on a polysilicon electrode using a salicide process. Even if the silicide layer on the polysilicon electrode is broken, the overall electrical connection of the gate electrode wiring is maintained by the lower polysilicon electrode. However, a resistance increase defect occurs at the position where the silicide layer is broken, thus causing a decrease in the yield and the reliability.
Similarly, a local resistance increase defect (soft-open defect) may occur at a certain position along a lower metal wiring, or in a contact connecting a source/drain impurity layer of a transistor, or the like, with an upper wiring layer. Thus, a variation (i.e., an increase) in the contact resistance, which is one form of a resistor variation, is a significant cause of a decrease in the yield and the reliability.
Recently, a semiconductor integrated circuit device uses a very large number of contacts therein. For example, in a 0.13 μm-rule chip having an area of about 40 mm2, the number of contacts used for the transistor-wiring layer connection is as large as about 20,000,000. Therefore, in a contact yield assessment using a monitoring device (assessment device), the assessment needs to be done for about 10,000,000 contacts.
Conventionally, the contact yield assessment has been done to detect complete line-break defects (hard-open defects). Specifically, for such a yield assessment, a large contact chain resistor pattern (including about 100,000 contacts) is provided to assess line-break defects (hard-open defects) in the contact chain.
FIG. 26A and FIG. 26B illustrate an example of a conventional contact chain resistor pattern, wherein FIG. 26A is a plan view and FIG. 26B is a cross-sectional view taken along line a-a′ of FIG. 26A.
Referring to FIG. 26A and FIG. 26B, a plurality of lower-layer wirings 3 formed from a polysilicon layer or an amorphous silicon layer are provided on a silicon substrate 1 with an insulating film 2 therebetween. An interlayer insulating film 4 is formed over the insulating film 2 and the lower-layer wirings 3, and a plurality of contact electrodes (contact holes) 5 connected to the lower-layer wirings 3 are formed in the interlayer insulating film 4. Moreover, a plurality of upper-layer metal wirings 6 are formed on the interlayer insulating film 4 so as to be connected to the contact electrodes 5. The lower-layer wirings 3 and the upper-layer metal wirings 6 are connected to each other via the contact electrodes 5 therebetween, thus forming a contact chain resistor pattern as illustrated in FIG. 26A. Note that the silicon substrate 1, the insulating film 2 and the interlayer insulating film 4 are not shown in FIG. 26A for the sake of simplicity. Alternatively, instead of providing the insulating film 2 and the lower-layer wiring 3, a transistor source/drain impurity layer may be formed on the surface of the silicon substrate 1 with contact electrodes being formed so as to connect the source/drain impurity layer with the upper-layer wirings.
The contact chain resistor pattern illustrated in FIG. 26A and FIG. 26B includes about 100,000 contacts. If a contact defect to be assessed is a complete line break (hard-open defect), it can be detected by detecting the contact chain resistance being infinitely high.
However, if only one contact becomes defective with the resistance thereof being increased to 10 times the normal value thereof, for example, the resulting variation in the overall resistance of the entire contact chain resistor pattern will be only about 1/10000 of the resistance increase defect. Therefore, it is difficult with an ordinary measurement method to detect such a resistance increase defect occurring in a single contact in the contact chain.
To address the problem, it has been proposed in the art to measure the resistance of each individual contact by providing a cross-contact array of 256 rows by 16 columns (a total of 4096 contacts) and using an 8-bit binary counter and a 256-bit decoder (see, for example, Takeshi Hamamoto, et al., “Measurement of Contact Resistance Distribution Using a 4k-Contacts Array”, IEEE Transactions on Semiconductor Manufacturing, Vol. 9, No. 1, February 1996, pp. 9-14 (hereinafter referred to as “Reference 3”)). With this method, it is possible to detect a resistance abnormality of a small resistance variation and thus to assess the yield.
However, the assessment of the resistance increase defects (soft-open defects) as described above is more difficult than the assessment of complete line-break defects (hard-open defects). For example, a line-break defect results in a very high or infinitely high electrical resistance, whereby it is possible to perform the defect assessment and the defect density assessment by virtually routing a very long line as described in Reference 1. However, it is difficult to detect resistance increase defects (soft-open defects) even by performing the defect assessment by virtually routing a very long line. This is because a resistance increase at the position of a soft-open defect will be inconspicuous in the overall resistance of the long line, whereby it is not possible to detect the resistance increase.
The methods described in Reference 2 and Reference 3 are disadvantageous in that they result in a very long process TAT (turn-around time) for providing the contact array, or the like. With these conventional techniques, the process TAT for providing the assessment device will be as long as that for making a semiconductor integrated circuit device, whereby the feedback of the assessment results for improving the process will take a very long time.